1. Field of the Invention
The present invention relates to a digital TV receiver, and more particularly, to an inverse discrete cosine transform (IDCT) apparatus.
2. Discussion of the Related Art
Generally, a moving picture experts group (MPEG)-2 specification is used for compression encoding of a digital image of a digital TV. In a basic concept of image compression, discrete cosine transform (DCT) and quantization are used to remove spatial redundancy. Also, a motion estimation-compensation method is used to remove temporal redundancy. The DCT is a method of removing correlation of spatial data through 2-dimensional orthogonal transform. After dividing an image frame into blocks having a uniform size, which do not overlap, pixels of the respective blocks are converted into a frequency region.
In the MPEG-2 specification, the size of such a DCT block is defined as 8*8 (block). The characteristic of the DCT block converted into the frequency region is that coefficients are mainly distributed in a low frequency region. This means that it is possible to compress data to be encoded by appropriate quantization and run-level coding of the DCT coefficients.
Therefore, in the digital TV receiver, an original image is recovered through performing of motion compensation, inverse quantization, and IDCT using motion vectors and DCT coefficients transmitted from a transmitter.
FIG. 1 is a block diagram illustrating a structure of a video decoder of a common digital TV receiver for recovering a video stream.
The function of the video decoder as shown in FIG. 1 is divided into the decompression with respect to the temporal compression and the recover with respect to space compress. The recover for the time compress is a portion performing the motion estimation-compensation by using a motion vector outputted from a variable length decoder (hereinafter refer to “VLD”) 101. The decompression for the spatial compression is a portion performing the IDCT after performing the inverse scan and the inverse quantization by using the DCT coefficient and the quantization value outputted from the VLD 101.
By referring to FIG. 1, a transmitted video bit stream is variable length decoded by a VLD 101 and is divided into the motion vectors, the quantization values, and the DCT coefficients. The quantization values and the DCT coefficients are outputted to an inverse scanner/inverse quantizer (IS/IQ) 102. The motion vectors are outputted to a motion compensation section 105.
The IS/IQ 102 uses a zigzag scan manner or an alternate scan. The IS/IQ 102 performs an inverse scan of inputted DCT coefficients in a raster scan manner, performs an inverse quantization of the inversely scanned DCT coefficients according to the quantization values, and outputs the inversely quantized DCT coefficients to an IDCT apparatus 104 through a coefficient buffer 103.
The IDCT apparatus 104 performs an inverse discrete cosine transform (herein after refer to ‘IDCT’) of the inversely quantized DCT coefficients, and outputs the DCT coefficients to an MB adder 107. A value outputted from the IDCT apparatus 104 to the MB adder 107 is a difference value between the pixels of the prior block and the pixels of present block.
The motion compensation section 105 performs motion compensation of the current pixel value using the motion vector and a previous frame pre-stored in a frame memory 100, and outputs the current pixel value to the MB adder 107 through a prediction buffer 106. At that time, the output value from prediction buffer 106 to the MB adder 107 is a compensated value for the present pixel.
The MB adder 107 adds the inverse discrete cosine transformed result value to the motion compensated result value in the unit of macro block and outputs the same. Thus, a recovered complete image corresponding to the final pixel value is outputted to a display device, and is stored in the frame memory 100 through a storage buffer 108 for motion compensation for the next block pixels. Here, the frame memory 100 has a storage capacity as the unit of frame.
At this time, a 54 MHz clock is used as a overall operation clock of the video decoder of FIG. 1 for high-speed image recovery of the digital TV receiver excluding the IDCT apparatus 104. In the video decoder, image recovery is consisted of the unit of macro blocks and the recovering process of data is basically performed in the unit of four pixels and four coefficients. However, regardless of following detailed description, the IDCT apparatus 104 performs the IDCT in a eight-coefficient unit.
The IDCT of the IDCT device will be described in detail as follow.
The IDCT apparatus 104 mainly performs 2-dimensional IDCT of the inputted DCT coefficients. The IDCT is a main factor of affecting image recovering performance of the digital TV set.
However, in the 2-dimensional IDCT, a plurality of mathematical operations should be performed.
The 2-dimensional IDCT performs 1-dimensional IDCT with respect to a column, transposes the column, and then also performs 1-dimensional IDCT with respect to a row.
The following equation 1 is a matrix expression of 2-dimensional IDCT.Z=ATXA  [Equation 1]
The equation 1 illustrates the 2-dimensional IDCT. In the equation 1, if “ATX” is transposed into “Y”, the equation 1 comes to “Z=YA=(ATYT)T”. then if the 2-dimensional IDCT is divided into 1-dimensional IDCT respectively, each 1-dimensional IDCT is illustrated as shown below.
Column IDCT(1-dimension): Y=ATX
Row IDCT(1-dimension): Z=(ATYT)T 
In the equation 1, A is a cosine constant matrix and AT is a transpose matrix of the cosine constant matrix.
Return to the description of the 2-dimensional IDCT, the 2-dimensional IDCT is performed by performing the 1-dimensional IDCT using the transpose matrix(AT) of a cosine constant for a column as illustrated in the Equation 1, transposing the result of the above-performed 1-dimensional IDCT, and is completed by performing the 1-dimensional IDCT on a row. At this time, the matrix expression of the IDCT is divided into an even matrix and an odd matrix by using orthogonality and symmetry of the transpose matrix of the cosine constant.
The following Equation 2 represents a cosine constant value. The equation 3 illustrates the 1-dimensional IDCT represented by the even matrix and the odd matrix.
                              [          abcdefg          ]                =                  [                      cos            ⁢                          π              4                        ⁢            cos            ⁢                          π              16                        ⁢            cos            ⁢                          π              8                        ⁢            cos            ⁢                                          3                ⁢                π                            16                        ⁢            cos            ⁢                                          5                ⁢                π                            16                        ⁢            cos            ⁢                                          3                ⁢                π                            8                        ⁢            cos            ⁢            7            ⁢                          π              16                                ]                                    [Equation 2]                                          [                                                                                          Y                    ⁡                                          (                      0                      )                                                        ,                                      Y                    ⁡                                          (                      7                      )                                                                                                                                                                Y                    ⁡                                          (                      1                      )                                                        ,                                      Y                    ⁡                                          (                      6                      )                                                                                                                                                                Y                    ⁡                                          (                      2                      )                                                        ,                                      Y                    ⁡                                          (                      5                      )                                                                                                                                                                Y                    ⁡                                          (                      3                      )                                                        ,                                      Y                    ⁡                                          (                      4                      )                                                                                                    ]                =                                                            1                2                            ⁡                              [                                                                            a                                                              c                                                              a                                                              f                                                                                                  a                                                              f                                                                                      -                        a                                                                                                            -                        c                                                                                                                        a                                                                                      -                        f                                                                                                            -                        a                                                                                    c                                                                                                  a                                                                                      -                        c                                                                                    a                                                                                      -                        f                                                                                            ]                                      ⁡                          [                                                                                          X                      ⁡                                              (                        o                        )                                                                                                                                                        X                      ⁡                                              (                        2                        )                                                                                                                                                        X                      ⁡                                              (                        4                        )                                                                                                                                                        X                      ⁡                                              (                        6                        )                                                                                                        ]                                ±                                                    1                2                            ⁡                              [                                                                            b                                                              d                                                              e                                                              g                                                                                                  d                                                                                      -                        g                                                                                                            -                        b                                                                                                            -                        e                                                                                                                        e                                                                                      -                        b                                                                                    g                                                              d                                                                                                  g                                                                                      -                        e                                                                                    d                                                                                      -                        b                                                                                            ]                                      ⁡                          [                                                                                          X                      ⁡                                              (                        1                        )                                                                                                                                                        X                      ⁡                                              (                        3                        )                                                                                                                                                        X                      ⁡                                              (                        5                        )                                                                                                                                                        X                      ⁡                                              (                        7                        )                                                                                                        ]                                                          [Equation 3]            
As descibed above, the IDCT appartaus 104 for the 1-dimensional IDCT represented by the multiplication of the even matrix by the odd matrix simultaneously receives eight coefficients as inputs and performs the corresponding multiplication.
Therefore, the IDCT apparatus 104 used in a conventional video decoder has a plurality of multiplexers that are arranged in parallel through various stages in order to satisfy a digital TV image recovery performance.
At this time, an algorithm for fast calculation of a multiplexer may be used. A Booth algorithm or an improved radix-2 multi-bit coding algorithm may be used.
If the IDCT apparatus 104 as described in FIG. 1 supports a high-speed IDCT, the IDCT apparatus 104 operates in 50 MHz and can perform up to a performance of 400M samples/sec. However, for the operation of the high-speed IDCT, the size of a circuit is very large.
However, since the performance of the IDCT apparatus satisfying the performance of the digital TV receiver is enough when it is 200M samples/sec, in the conventional video decoder mounted in the digital TV receiver, 27 MHz as an operation clock of the IDCT apparatus is used. Then, it is possible to obtain 216 sample rate
Like this, in the event of using 27 MHz as the operation clock of the IDCT apparatus, the size of the logic circuit necessary to obtain the required sample/sec is reduced.
However, there are still problems to satisfy the digital TV receiver image recovery performance by the IDCT apparatus operated by 27 MHz.
The problem is that a section 202 for performing the IDCT receives and processes data inputted in the unit of eight coefficients.
Therefore, as shown in FIG. 2, the IDCT apparatus installed inside the conventional video decoder must demultiplex four data items by eight data items in an input and must multiplex eight data items by four data items in an output using a demultiplexer 201 and a multiplexer 203 again. Here, the demultiplexer 201 demultiplexes the four data to be inputted into eight data, while the multiplexer 203 multiplxes the eight data to be outputted into four, data.
FIG. 3 illustrates a timing chart of the demultiplexer 201 for controlling the input of an IDCT section 202. FIG. 4 illustrates a timing chart of the multiplexer 203 for controlling the output of the IDCT section 202.
By referring FIGS. 2 and 3, coefficient data items c_d0 to c_d3 inputted to the demultiplexer 201 by an overall operation clock vdclk of the apparatus are demultiplexed to eight data x0 to x7 by the clock idctclk of the IDCT section 202.
By referring FIGS. 2 and 4, the pixel values z0 to z7 outputted from the IDCT section 202 by the clock idctclk of the IDCT section 202 are multiplexed to four pixel data items I_d0 to I_d3 by an overall operation clock vdclk. The multiplexed data are outputted to the MB adder 107 as shown in FIG. 1.
Here, the overall operation clock vdclk is 54 MHz and the operation clock idctclk of the IDCT section 202 is 27 MHz.
Summing up, the IDCT apparatus performing the IDCT through the mathematical operation such as equation 3 in the conventional video decoder simultaneously receives eight inputs using the demultiplexer 201, performs the multiplication operations of the even matrix and the odd matrix, and outputs eight inverse discrete cosine transformed pixels every clock through the multiplexer 203 in order to satisfy the required performance of the digital TV receiver.
As described above, by the addition of the demultiplexer and the multiplexer to the IDCT apparatus causes an amount of logic to significantly increase in implementing the circuit. Also, as the IDCT apparatus uses the operation clock different from operation clock of another sections of the overall video decoder, timing control must be performed, while paying much attention to an interface with the IDCT apparatus and another sections. Further, there is a need of a further clock generator.
The IDCT apparatus of the conventional video decoder has disadvantages that multiplier is increased according to the processing of eight coefficients and a logic circuit is increased in implementing an ASIC as unnecessary multiplexer and demultiplexer are added.